Mode Error Flag in SMR3 register while setting up SPI(Special Mode 2)

I am trying to get SPI going on UART2 in a M32C87. I have checked all the register set-ups many times and cannot get a clock even generated when in Master Mode. All I can see that might indicate teh reason is teh Mode Erro Flag is set in U2SMR3. Does anyone have a clue what I might be doing wrong? There seems to be no available sample code to compare against or use as a starting point. My code is below:

Init Code . . .

            DISABLE_IRQ   // Disable interrupts

           u2mr = 0x01;     
   
            //  00000001
            //  8 bit mode, internal clock(master), one stop, no parity, no polarity inversion
            //
            //  b2:b0       SMD2:0    selects clock synchronous mode
            //  b3      CKDIR       0=master (1=slave)   
            //  b4      STPS        one stop bit (NA)
            //  b5      PRY         odd parity (NA)
            //  b6      PRYE  diable parity (NA) 
            //  b7      IOPOL  data not inverted

           u2smr = 0x00;  
   
            //  00000000             not needed for SPI

           u2smr2 = 0x00;  
   
            //  00000000             not needed for SPI

            u2smr3 = 0x03;      
           
            //  00000111            
            //
            // sse_u2smr3
            // ckph_u2smr3
            // dinc_u2smr3
            // nodc_u2smr3
            // err_u2smr3
            // dl0_u2smr3
            // dl1_u2smr3
            // dl2_u2smr3

           u2smr4 = 0x00;  
   
            //  00000000             not needed for SPI

            u2c0 = 0xf4;   
         //  MSB first, n channel output, CTS/RTS disabled, f1 clock source
            //  b1:b0    CLK1:0  COUNT SOURCE DIVIDED BY 1
         //  b2   CRS     CTS RTS ENABLED WHEN CRD=0 
         //  b3   TXEPT  TRANSMIT REGISTER EMPTY FLAG          
         //  b4   CRD     CTS/RTS FUNCTION DISABLED
         //  b5    NCH     DATA OUTPUT SELECT BIT
         //  b6   CKPOL  CLOCK POLARITY SELECTED,TX FALLING EDGE,RX RISING EDGE 
         // b7   UFORM  MSB FIRST

         u2brg = 0x01; // Fast!
//         u2brg = (_UBYTE)(((f1_CLK_SPEED/16)/SPI_BAUD_RATE)-1); 
 
         //  bit rate can be calculated by:
         //  bit rate = ((BRG count source / 16)/baud rate) - 1
         //  ** the value of BCLK does not affect BRG count source

         u2c1 = 0x10; // Turned off for now  
         // 00010000 UART0 transmit/receive control register 1
         //  b0      TE   Transmit Enable Bit
         //   b1     TI   Transmit buffer empty flag,
         //   b2     RE   Receive enable bit,
         //   b3       RI   Receive complete flag,
         //   b5:b4        Reserved, set to 0
         //   b6      U0LCH  Data logic select bit,
         //   b7      U0ERE  Error signal output enable bit,

            s2tic = 0x04;
            // 00000010 Interrupt not requested (yet) and level 4

            // ilvl0_s2tic
            // ilvl1_s2tic
            // ilvl2_s2tic
            // ir_s2tic   

            s2ric = 0x04;
            // 00000010 Interrupt not requested (yet) and level 4

            // ilvl0_s2ric
            // ilvl1_s2ric
            // ilvl2_s2ric
            // ir_s2ric   

            // Pin Settings
            // TXD2
            pd7_0 = 1; // output
            ps1_0=1;
            psl1_0 = 0;
            psc_0 = 0;
            // RXD2
            pd7_1 = 0; // input
            ps1_1 = 0;
            // CLK2
            pd7_2 = 1; // output
            ps1_2 = 1;
            psl1_2 = 0;
            psc_2 = 0;
            
           ENABLE_IRQ 

Turn on code . . .

    switch (port)
    {
    case 0:
        if (state == ON)
        {
            u2c1 |= te_u2c1; // Turn on transmit   
            u2c1 |= re_u2c1; // Turn on receive   
        }
        else
        {
            u2c1 &= ~te_u2c1; // Turn off transmit   
            u2c1 &= ~re_u2c1; // Turn off receive   
        }
    break;

Thanks for any suggestions.

stw