SH3 Writeback Cache Problems

Using an SH7727 in an embedded application, we are having a number of unexplained resets and exceptions when we have the cache running in write-back mode.  These problems go away when we run the cache in write-through mode.

An article in the Microsoft Knowledge Base ( http://support.microsoft.com/kb/199541 ) indicates that a problem exists with the SH3 cache.  Does anyone have any more information on this?

Are you using WinCE? Which hardware reference platform do you have?

Have you checked the errata on the 7727 to see if this chip is affected? I don't see one, although there is a "technical update" about the use of the DMA. it says to use a workaround if you use DMA with certain clock setup parameters:

(1) Please do not use the DMAC during the sleep mode, or set ratio Iø:Bø=1:1 before the sleep mode.

(2) Please do not use the DMAC when only the IFC[2:0] is modified and it is not Iø:Bø=1:1.

We are not using WinCE or any standard hardware reference platform.  We are using Express Logic ThreadX and the SH7727 CPU in a ground up custom design.  This is not our first SH3 design, but it is the first time we have had reason to suspect a problem with the cache.

Yes, we have thoroughly examined all available errata and Technical Updates.  Regarding the DMAC issues you raised, (1) we are not using sleep mode and (2) our Iø:Bø = 4:1.

The 7727 is not a new chip, so I would expect any issues with the cache to have been documented in a tech update. I searched everywhere I could.

Have you tried fiddling with the external bus frequency? If it isn't too difficult, you may want to check to see if the cache works better at other external bus frequencies.

Thanks for the reply.  I tried cutting the external bus frequency (Bø) in half, keeping other frequencies (Iø and Pø) the same.  It seemed to fail a little more often this way.

Meanwhile, we are taking another look at our SDRAM timing (connected to Area 3).  So far we don't see any obvious problems.

We have a Hitachi / Renesas App note ( http://documentation.renesas.com/eng/products/region/rte/mpumcu/apn/app12810.pdf ) which we obtained from the eu.renesas.com web site.  The App note is called "SH3(-DSP) Interface to SDRAM" and on page 55, it refers to a spreadsheet, which can be used to confirm SDRAM timing.  Do you know where I can get a copy of the spreadsheet?