I/O speed

Hello friends

I'm new in this forum. I ask if anyone have suggestion about this.

I  have write a very little program for SH7211 and RSK board, for test the I/O speed.  the loop are the following

while (1) {

PB.DR.BIT.B10=0;

PB.DR.BIT.B10=1;

}

But I get in oputput only 2.5 MHz square wave frequency, very low frequency for this high speed microcontroller. I'm using the Debug_HMon. The same result I have if compile in RELEASE.

Thanks in avance for your Help.

I have set the   frequncy in this way.

  /* Set CPU PLL operating frequencies.*/

   /* Stop WDT by writing 0 to all un-reserved bits with
       the upper byte containing H'A5 */
    WDT.WRITE.WTCSR = 0xA518;

    /* The perhiperal clock is 10MHz at start-up. To make a 10mS clock
       settling delay it must be set to count 100,000 cycles (10mS / (1 / 10MHz)).
       To do this the peripheral clock is divided by 1024 (CKS = B'101 or H'5),
       and the WTCNT register is loaded with 157 (255 - (100,000 / 1024)).
       First set the peripheral clock divisor to H'5 for division by 1024 */
    WDT.WRITE.WTCSR = 0xA51D;

    /* Set WCTNT to 157 */
    WDT.WRITE.WTCNT = (0x5A00 + 157);

 CPG.FRQCR.WORD = 0x1303; // 160 MHz Clock 40 MHz for peripherial.

 /* Configure MTU2 clock
  B7:B6 - Source clock select - PLL1 output clock
  B5:B2 - Reserved
  B1:B0 - Division Ratio Select - 1/2 time */

 CPG.MCLKCR.BYTE = 0x43;

 /* Configure MTU2 clock
  B7:B6 - Source clock select - PLL1 output clock
  B5:B2 - Reserved
  B1:B0 - Division Ratio Select - 1/4 time */

 CPG.ACLKCR.BYTE = 0x43;

The max I/O freq is going to be limited by the internal peripheral bus frequency. Your output GPIO freq is probably limited to 20 or 40Mhz. A harware timer toggling an I/O might end up being faster.

With regard to your code: I'd suggest trying to write 16 bit or 32 bit values to the I/O ports you are toggling. The C compiler is probably doing things with the 0 and 1 type values that are adding delay. You'll be able to check this by looking at the disassembly code in the HEW editor window (assuming you've got a debugging connection or simulator session). You'll note that the looping also adds overhead.

Thanks Calvin.

I have changed the loop in this way:

while (1) {
 90   PB.DR.LONG=0xFFFFFBFFL;
      FFF804AA 2C22              MOV.L     R2,@R12
  91   PB.DR.LONG=0xFFFFFFFFL;
     FFF804AC AFFD              BRA       @H'FFF804AA:12
     FFF804AE 2CD2              MOV.L     R13,@R12
  92
  93  }

The speed increase a little now generate a square wave of 3.597 MHz always slow, for 40MHz PClock and  160MHz IClock.

I don't think that HMON slows your software down. I don't see how HMON could slow down every instruction.

But I would like to know how you initialise the processor. Which external clock do you use? What do you write to FRQCR to initilise all internal clocks?

HI FrankL

I use this setting, supplyed whit the tutorial of the RSK the clock is external 10 MHz:

void ConfigureOperatingFrequency(void)
{
/* Set CPU PLL operating frequencies.*/

   /* Stop WDT by writing 0 to all un-reserved bits with
       the upper byte containing H'A5 */
    WDT.WRITE.WTCSR = 0xA518;

    /* The perhiperal clock is 10MHz at start-up. To make a 10mS clock
       settling delay it must be set to count 100,000 cycles (10mS / (1 / 10MHz)).
       To do this the peripheral clock is divided by 1024 (CKS = B'101 or H'5),
       and the WTCNT register is loaded with 157 (255 - (100,000 / 1024)).
       First set the peripheral clock divisor to H'5 for division by 1024 */
    WDT.WRITE.WTCSR = 0xA51D;

    /* Set WCTNT to 157 */
    WDT.WRITE.WTCNT = (0x5A00 + 157);

/*Note : Changes to the peripheral clock will require changes to the debugger and flash
kernel BRR settings. REF: HMONSerialConfigUser.h define for SCI_CFG_BRR */
 /* B15:B13 - Reserved - set to 0
  B12 - Clock Output Enable
  B11:B10 - Reserved - set to 0
  B9:B8 - Frequency multiplication ratio of PLL circuit 1 - 4 times
  B7 - Reserved - Set to 0
  B6:B4 - Internal Clock (Iö) Frequency Division Ratio - 1/4 time
  B3 - High or LOW frequency mode - Select high frequency mode.
  B2:B0 - Peripheral Clock (Pö) Frequency Division Ratio - 1/4 time */

 CPG.FRQCR.WORD = 0x1303;

 /* Configure MTU2 clock
  B7:B6 - Source clock select - PLL1 output clock
  B5:B2 - Reserved
  B1:B0 - Division Ratio Select - 1/2 time */

 CPG.MCLKCR.BYTE = 0x43;

 /* Configure MTU2 clock
  B7:B6 - Source clock select - PLL1 output clock
  B5:B2 - Reserved
  B1:B0 - Division Ratio Select - 1/4 time */

 CPG.ACLKCR.BYTE = 0x43;
}

I have test all configuration of FRQCR registrer and the maximun frequency for square wave generation is 3.597 MHz.

Do you have made one test that switch on/off one bit? what frequency you have see?

Thanks

I don't have a 7211. I only have a 7203 running with external memory. This one is a little bit slower on the peripheral bus than your 7211.

When I run the pripheral bus at 33MHz I see output pulses of 420ns.

If I run the pripheral bus at 16.66MHz the output pulses are 480ns.

But when I use the timer output of MTU2 I get the full speed with 30ns pulse width. If you are interested, this is my initialisisation of the timer.

    /* Stops the timer from counting */
    MTU2.TSTR.BIT.CST2 = 0;
    /* Set timer control register
        b2:b0    TPSC [2:0]    Time Prescaler, Internal/1
        b4:b3    CKEG [1:0]    Clock Edge, falling
        b5:b7    CCLR [2:0]    Counter Cleared on compare match A    */
    MTU2.TCR_2.BYTE = 0x28;
    /* Set timer in Normal mode. */
    MTU2.TMDR_2.BYTE = 0x00;
    /* Configure the port pin    */
    PORT.PDIORL.BIT.PD6IOR = 0x01;
    PORT.PDCRL2.BIT.PD6MD = 0x05;   
    /* Configure Timer I/O Control Register   
        B7:B4    IOB3:IOB0 - Not used
        B3:B0    IOA3:IOA0 - Toggle output on compare match    */
    MTU2.TIOR_2.BYTE = 0x03;
    /* Set the period by setting the initial value
       1/(33.33 MHz(Pphi)/1) * 1 = 30ns pulse width    */
    MTU2.TGRA_2.WORD = 0x0000;

Hi FrankL.

I have made the square wave generation only for the the i/o speed of this fast (?) cpu. But the 3.3 MHz that I have in output whit 40MHz peripheral clock is too slow.

Maybe you are testing the 7211 in a way that doesn't make sense for the application. I think that your question should be: "how can I receive a 6 Mhz serial data stream from an external device (dvb-s) tuner"  Based on your postings we all thought you wanted to generate a square wave - which is usually done with a timer.

Communication should be done with a serial peripheral, since they are able to do fast data transfers without bit-banging the data. The peripherals have buffers, etc. for fast low-overhead communications. The 7211 has 4 independent channels.

HI.

Do you only receive data, or is this bi-directional?

Do you ahve a clock signal in parallel?

Would it be possible to use the DMA controller for data transfer, may be triggered by a timer interrupt?

I receive only.

I have 8 bit data,1 bit clock and 1 bit start packet (188/204 byte for packet).

I have to analyze the packet received, and if is the SI (service information) i manage it, very easy program. I have made the software and tested it whit one 8051 silicon labs, and work fine up to  1 MHz clock

I have tested te same software whit the SH7211 and have the same result. This because the reading port is to slow 200 ns

Then it should be possible to use the clock signal as trigger for the DMA controller, and read the 8 bit data by DMA. I'm not sure how to integrate this start packet signal. If it is long enough you could use it to enable the DMA in an interrupt routine.

This should spped up data receive a lot.

Ok Frank. Your suggestion is one solution. The start packet in long one period of clock data.

I suppose that I have to inizialize the DMA source address whit  the address of  input port  where I connect the 8 bit data  and the destination address whit  the andress of memory buffer. It's correct?