Maximum Input Clock Restriction

Understand from the user manual that for TCLKA: 

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower

pulse widths.

So if my clock is run at 160Mhz, and I am using single-edge detection, so the maximum clock input for TCLKA = 160/1.5= 106.67Mhz ? Anybody can help on this? Thanks.

This 1.5 cycles is 1.5 cycles of the peripheral clock, NOT of internal clock. If the max. peripheral clock is 40MHz, TCLKA input is max 26.6MHz

Thanks for reply.

So even though I use the 160MHz crystal for the CPU main clock source, the TCLKA input max still 26.6Mhz(since the peripheral clock is 40Mhz)?

Correct.

I am doing a sampling signal from video which has frequecy at 28Mhz. So in order to capture it fully without losses, can I still use TCLK1 as it max input is only 26.67Mhz?

Btw do you have any video sampling application by using SH7211?